Moore’s Law will continue to provide exponentially increasing transistor integration capacity to integrate diverse functions in a system, enabling unprecedented compute capability, and making it ubiquitous to further enrich our lifestyles. However, the same physics that made this possible also pose some barriers, namely energy consumption and limitations of system interconnections. Supply voltage reduction has slowed down for numerous reasons, resulting in higher energy with higher levels of transistor integration. Higher integration also demands more interconnections, which have started hitting the fundamental limits of physics.
The Centip3De design is truly a marvel of an energy-efficient system demonstrating two key concepts to address these challenges, namely near-threshold computing (NTC), and 3D integration.
NTC calls for reducing the supply voltage, reducing the frequency of operation to improve energy efficiency—a little counterintuitive. But if you think about it, the frequency reduces almost linearly while the energy reduces quadratically, providing substantial gain in energy efficiency. But, hey, the critics would say, NTC would employ substantially more transistors in a system to provide the same throughput! That is exactly what Moore’s Law and transistor integration capacity provides; if you do not use it with NTC then you will not get to use it because of energy consumption. Employing NTC may sound simple, but it needs careful system optimization. Supply voltage reduction reduces active energy, but the leakage energy starts becoming a substantial portion of the total energy, thus requiring a detailed system-level analysis and architecture conducive for NTC.
The Centip3De system implements a many-core system, architected with 3D integration in mind, incorporating processor chips, cache chips, and DRAM chips into a 3D cube—all designed for NTC operation.
3D integration is realized by stacking thinned chips and interconnecting them with vias (thin insulated vertical wires); integrating chips in the third dimension, and hence the name. This 3D integration substantially reduces interconnect length, decrease signal delay, and also saves interconnect energy. Additionally, this integration allows you to combine a system with dissimilar technologies, such as DRAM, SRAM, and logic chips in one system stack—in stark contrast to integrating all these technologies into a single process that is prohibitively expensive. Once again, the system architecture and the design must comprehend 3D integration from day one.
The Centip3De system described in the following paper implements a many-core system, architected with 3D integration in mind, incorporating processor chips, cache chips, and DRAM chips into a 3D cube—all designed for NTC operation, demonstrating a wide operating range. Clearly, this is a novel approach to system design with two promising technologies, and I would not be surprised to see it catch on quickly!
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