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Research and Advances

Amortized efficiency of list update and paging rules

In this article we study the amortized efficiency of the “move-to-front” and similar rules for dynamically maintaining a linear list. Under the assumption that accessing the ith element from the front of the list takes &thgr;(i) time, we show that move-to-front is within a constant factor of optimum among a wide class of list maintenance rules. Other natural heuristics, such as the transpose and frequency count rules, do not share this property. We generalize our results to show that move-to-front is within a constant factor of optimum as long as the access cost is a convex function. We also study paging, a setting in which the access cost is not convex. The paging rule corresponding to move-to-front is the “least recently used” (LRU) replacement rule. We analyze the amortized complexity of LRU, showing that its efficiency differs from that of the off-line paging rule (Belady's MIN algorithm) by a factor that depends on the size of fast memory. No on-line paging algorithm has better amortized performance.
Research and Advances

An inverted taxonomy of sorting algorithms

An alternative taxonomy (to that of Knuth and others) of sorting algorithms is proposed. It emerges naturally out of a top-down approach to the derivation of sorting algorithms. Work done in automatic program synthesis has produced interesting results about sorting algorithms that suggest this approach. In particular, all sorts are divided into two categories: hardsplit/easyjoin and easysplit/hardjoin. Quicksort and merge sort, respectively, are the canonical examples in these categories. Insertion sort and selection sort are seen to be instances of merge sort and quicksort, respectively, and sinking sort and bubble sort are in-place versions of insertion sort and selection sort. Such an organization introduces new insights into the connections and symmetries among sorting algorithms, and is based on a higher level, more abstract, and conceptually simple basis. It is proposed as an alternative way of understanding, describing, and teaching sorting algorithms.
Research and Advances

Computer professionals whose scientific freedom and human rights have been violated—1984: a report of the ACM committee on scientific freedom and human rights

This is the third report prepared by the ACM Committee on Scientific Freedom and Human Rights (CSFHR). The first was published in the March 1981 Communications and the second in the December 1982 issue. This report is an update. Since the committee intends to publish future updates, it would appreciate receiving further information about computer scientists whose rights have been violated. Such information should be sent to: Jack Minker, Vice-Chairman, Committee on Scientific Freedom and Human Rights, Department of Computer Science, University of Maryland, College Park, MD 29742.Because those whose scientific freedom or human rights have been violated derive sustenance and support from contacts with their colleagues, the CSFHR has established a program in which ACM chapters “adopt” individual scientists and correspond with them. Such correspondence should touch on the personal and scientific and not discuss political matters. These letters greatly improve the morale of the recipients and are one of the few ways they can keep current with computer science and technology. This CSFHR program is directed by Helen Takacs (P.O. Drawer CS, Mississippi State, MS 39762).
Research and Advances

Reduced instruction set computers

Reduced instruction set computers aim for both simplicity in hardware and synergy between architectures and compilers. Optimizing compilers are used to compile programming languages down to instructions that are as unencumbered as microinstructions in a large virtual address space, and to make the instruction cycle time as fast as possible.
Research and Advances

The cosmic cube

Sixty-four small computers are connected by a network of point-to-point communication channels in the plan of a binary 6-cube. This “Cosmic Cube” computer is a hardware simulation of a future VLSI implementation that will consist of single-chip nodes. The machine offers high degrees of concurrency in applications and suggests that future machines with thousands of nodes are both feasible and attractive.

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