E. S. Davidson
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Computer system design using a hierarchical approach to performance evaluation
The concept of a hierarchy of performance models is introduced. It is argued that such a hierarchy should consist of models spanning a wide range of accuracy and cost in order to be a cost-effective tool in the design of computer systems. Judicious use of the hierarchy can satisfy the conflicting needs of high accuracy and low cost of performance evaluation. A system design procedure that uses the hierarchy is developed.
The concepts developed are illustrated by applying them to a case study of system design. The results of optimizations conducted using a two-level performance model hierarchy and a simple cost model are discussed. In almost all the experiments conducted, the optimization procedure converged to a region very close to a locally optimum system. The efficiency of the procedure is shown to be considerably greater than that of the brute force approach to system design.
Performance evaluation of highly concurrent computers by deterministic simulation
Simulation is presented as a practical technique for performance evaluation of alternative configurations of highly concurrent computers. A technique is described for constructing a detailed deterministic simulation model of a system. In the model a control stream replaces the instruction and data streams of the real system. Simulation of the system model yields the timing and resource usage statistics needed for performance evaluation, without the necessity of emulating the system. As a case study, the implementation of a simulator of a model of the CPU-memory subsystem of the IBM 360/91 is described. The results of evaluating some alternative system designs are discussed. The experiments reveal that, for the case study, the major bottlenecks in the system are the memory unit and the fixed point unit. Further, it appears that many of the sophisticated pipelining and buffering techniques implemented in the architecture of the IBM 360/91 are of little value when high-speed (cache) memory is used, as in the IBM 360/195.
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