Benjamin C. Lee – Communications of the ACM

Research and Advances Feb 1 2019

Distributed Strategies for Computational Sprints

We describe a computational sprinting architecture in which many, independent chip multiprocessors share a power supply and sprints are constrained by the chips' thermal limits and the rack's power limits.

Architecture and Hardware

Author Archives

Research and Advances Oct 1 2011

Understanding Sources of Ineffciency in General-Purpose Chips

To better understand what improvement in processor efficiency is possible, we quantify the performance and energy overheads of a 720p HD H.264 encoder running on a CMP system. We explore methods to eliminate these overheads by transforming the CPU into a specialized system for H.264 encoding.

Architecture and Hardware

Research and Advances Jul 1 2010

Phase Change Memory Architecture and the Quest For Scalability

Memory scaling is in jeopardy as charge storage and sensing mechanisms become less reliable for prevalent memory technologies. In contrast, phase change memory relies on programmable resistances, as well as scalable current and thermal mechanisms.

Architecture and Hardware

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