The computing world has always relied on advances in semiconductors. Over the decades, smaller and more efficient transistor designs have produced faster, more powerful, more energy-efficient microchips. This has fueled incredible advances in everything from supercomputing and clouds to smartphones, robotics, virtual reality, augmented reality, additive fabrication, and the Internet of Things (IoT).
The march toward more sophisticated microprocessors has continued unabated for decades. However, Moore’s Law, which states the number of transistors in an integrated circuit doubles approximately every one-and-a-half to two years, has begun to slow in recent years. The reason? It has become more difficult to use MOSFET (metal-oxide-semiconductor field-effect transistors) scaling techniques to achieve continued miniaturization. Many chips now contain 20 billion or more switches. Engineers are running into enormous challenges as they reach the physical limits of existing technology.
Figure. A 2017 scan of the IBM Research Alliance’s 5nm silicon nanosheet transistor containing 30 billion switches.
However, an emerging technology promises to change the equation. Nanosheet transistors, which also go by the names gate-all-around, multi-bridge channel, and nanobeam, push beyond today’s 7-nanometer (nm) node and into more-advanced 5 nm designs with performance boosts of approximately 40% and power consumption cuts of 75%. Samsung announced in May last year it had perfected nanosheet transistors and would be introducing them commercially in the first half of this year. “It’s a huge advance in the device structure itself. It will enable significant advances in computing,” says Mukesh V. Khare, a vice president at IBM Research.
Miniaturization Matters
Moore’s Law has served the semiconductor industry well since Intel co-founder Gordon Moore introduced the idea in 1965. Just over a half-century later, transistor designs appear to finally be approaching their physical limits—at least using current materials and designs. “We are reaching a quantum threshold where the transistors cannot get a lot smaller and we cannot keep on achieving gains at the speed of Moore’s Law,” explains Peide Ye, Richard J. and Mary Jo Schwartz Professor of Electrical and Computer Engineering at Purdue University.
Current transistors use a time-proven design based on MOSFET technology, which has been in use since 1959. While shapes and materials have advanced and changed over the years, the basic engineering remains the same. The design incorporates a gate stack, channel region, source electrode, and a drain electrode. The structure is designed to transport positive (p-type) or negative (n-type) charges. Together, they produce an integrated circuit (IC) needed for the complementary metal-oxide-semiconductor (CMOS) technology that powers computers and mobile phones.
Today’s designs place the gate stack directly above the channel area. The metal gate stack sits atop a dielectric material that conducts an electric field into the transistor channel region to accumulate or block charges that could flow through. In basic terms, this allows current to flow across the transistor and switch on and off as needed. The problem is that as these structures become smaller, it becomes more difficult to block the charge leak across the transistor. The resulting leakage leads to hotter, less power-efficient microchips. Engineers have approached this problem by making the channel region thinner and thinner.
Fin Field Effect Transistor (FinFET) technology is used in virtually all of today’s processors. It incorporates stacked sheets and a channel region that is tilted upward (think of it as a wall) to create a wider path for current. The gate and dielectric are placed over the fin so that it is surrounded on three sides instead of just one; this helps reduce current leakage. These three-dimensional (3D) designs, used by major semiconductor manufacturers, have shrunk from about 22 nm in 2011 to between 7 nm and 5 nm today. Unfortunately, they cannot be built at the 3-nm scale and accommodate current switching methods. “The leakage and power drain are simply too much for the technology to be viable at this scale,” says Dan Hutcheson, CEO of VLSI Research, Inc., a market research and consulting firm.
“Nanosheet transistors are creating a new ecosystem for device structure, modeling, process technology, and various materials.”
For years, researchers and engineers have known they were approaching the end of the road for current transistor designs. Although myriad tweaks, advances, and trade-offs have led to ongoing advances in central processing units (CPUs), graphics processing units (GPUs), and other chips, the need for radically different designs was completely apparent. Nanosheets extend performance by removing material between layers of other material and filling in the gaps with both metal and dielectric.
This leads to a smaller-scale design. What is more, “The gate is wrapping around all four sides of the silicon and the silicon channel thickness scaling is controlled by epitaxial growth, which moves things beyond nanometer control and into atomic level control,” Khare explains.
Beyond Silicon
At the heart of nanosheet transistors are new materials and radical design changes. Gary Patton, CTO and head of worldwide research and development at GlobalFoundries, has described them as “a smaller, faster, and more cost-efficient generation of semiconductors.” The technology, which IBM began researching in 2006 and which took shape under a public-private industry alliance, essentially creates a device architecture with stacked layers of silicon sheets by retaining the silicon layers from a superlattice structure that consists of alternating crystal layers of silicon and silicon germanium.
The significance of these new materials and designs, such as germanium, should not be minimized. Chipmakers have been forced to reduce clock speeds because of the enormous heat produced by high transistor density. However, by incorporating new materials and designs, it is possible to replace several slower processor cores with a single chip that operates as fast while generating less heat. In some cases, electrons can move more than 10 times faster in these semiconductor designs.
Nanosheet technology represents a remarkable advance in transistors. “These nanosheet layers are patterned lithographically to form gates that wrap around the junction between the source and drain by etching away unwanted material. This is done multiple times to form structures that look something like the center of a layer cake cut in thirds,” Hutcheson explains.
It is possible to place upward of 30 billion switches on a fingernail-sized chip. The gate surrounds the channel region in its entirety to deliver greater control than FinFET. This “stacked” structure supports far more advanced semiconductor fabrication processes. “When the industry figured out how to use certain chemistries to lay down substances at a single molecular level and then place others on top of it, the manufacturing process advanced radically,” Hutcheson says. “They were no longer painting on a thick surface. They could control the deposited material to a single atomic layer.”
The Endura Clover system from Applied Materials, for example, can apply up to 30 layers within a single stack only a few angstroms thick. This ensures an extremely high level of production quality.
To be sure, “Nanosheet transistors are far more than a technology iteration.
It is extending Moore’s Law for several more years. In fact, the design framework surrounding nanosheet transistors will allow researchers and engineers to develop even more advanced transistors and standard cells than FinFET technology allows, including flexibility in circuit design,” Khare says. “The industry is converging around this device structure and it is moving forward with fabs and production. Nanosheet transistors are creating a new ecosystem for device structure, modeling, process technology, and various materials.”
Of course, the transition will not happen overnight. The technology will require entirely new fabs and changes in distribution channels. “The cost of a new fab is in the $20-billion range, so it isn’t something to take casually. There’s an enormous amount of money and planning that must go into their transition,” says Purdue’s Ye.
While the first nanosheet transistors likely will appear from Samsung some time this year, it may take several more years before production scales up to support widespread adoption. Only Intel, Samsung, and Taiwan Semiconductor Manufacturing Co. (TSMC) have the means to handle this level of miniaturization. It is far more complicated than updating existing fabs. Chipmakers must build entirely new fabs with equipment and systems to handle the specialized nanosheet construction, at a cost that can reach $20 billion, Ye says.
Ultimately, the question is not whether nanosheet technology will impact the market, but rather when and how. “There’s no way to know when we will hit the crossover point and nanosheet transistors will become the dominant technology,” Khare says. “There are a lot of technical and economic issues that intersect with it. What’s clear is that we will see products emerging within a couple of years and they will impact many aspects of computing, from devices and datacenters to the edge of the network.”
Make no mistake, nanosheet transistors will lead to more powerful devices that utilize power far more efficiently—a key consideration in an era where battery life matters, energy costs are exorbitant, and climate change concerns are growing. The technology will introduce new and more advanced capabilities, particularly in the artificial intelligence arena, where advances in computing power can fuel exponential gains. Says Hutcheson, “We will have transistors that can handle heavy-duty artificial intelligence. The impact will ripple out to datacenters, smartphones, self-driving cars, and many other areas.”
Designs on the Future
Nanosheet transistors will shape the semiconductor industry for years to come. The technology takes aim at a fundamental problem, Khare says. “Integrated circuits (IC) have been stuck at the same power density for about a decade. It’s been impossible to remove more than about 100 watts per square centimeter.” Chip designers have focused on keeping heat buildup down, including limiting clock speed to 4 gigahertz or less and using slower multi-core designs that substitute a more-powerful single processor, but generate much less heat.
Nanosheets can break through this barrier with a more efficient transistor design combined with new material, like germanium. It could push the ranges further for power and energy consumption. This addresses a major problem in semiconductors: “As feature sizes shrink, conventional methods of manufacture fail to produce devices that work well electrically,” Hutcheson says. “With the tri-gate structure used on current devices, they can fail to switch on or off, because there is not enough surface area contacted by the gate, hence the need to wrap all four sides. There can also be power dissipation problems due to leakage. The reason why new materials are needed is that silicon can’t be deposited over a dielectric in a properly oriented crystalline form to form the junctions.”
The nanosheet technology also opens up new possibilities and opportunities within the semiconductor field, especially when combined with new materials. These design improvements also create more favorable economics for manufacturing because today’s technology is too expensive to produce with some of these materials, Hutcheson says.
In order to bump up clock speeds, Ye and others say it is necessary to produce more powerful and energy-efficient transistors than silicon alone can deliver. Consequently, he and others continue to research different materials and designs that can be used in the channel region. This includes germanium, as well as semiconductors built from indium gallium arsenide (InGaAs). Other researchers are exploring how combinations of germanium, indium arsenide, and gallium antimonide can offer even greater efficiencies in nanosheets and other semiconductor designs.
Researchers have found that electrons can move up to 10 times faster within these more-advanced semiconductors. The end result is chips that not only switch faster, but also operate at much lower voltage levels—thus enabling new types of functionality and features. These designs likely will introduce capabilities that we can’t imagine today. For now, chipmakers are sold on the concept. Most have already committed to using nanosheet transistors in their future designs.
Concludes Ye: “The combination of nanosheet transistors and advances in semiconductors will carry us far into the future. The technology will have a significant impact on computing.”
Further Reading
Ye, P., Ernst, T., and Khare, M.V.
The last silicon transistor: Nanosheet devices could be the final evolutionary step for Moore’s Law, IEEE Spectrum, Volume 56, Issue 8, August 2019. https://ieeexplore.ieee.org/abstract/document/8784120
Moayed, M.M.R., Bielewicz, T., Noei, H., Stierle, A., and Klinke, C.
High-Performance n- and p-Type Field-Effect Transistors Based on Hybridly Surface-Passivated Colloidal PbS Nanosheets. Advanced Functional Materials. Volume 28, Issue 19, May 9, 2018. https://onlinelibrary.wiley.com/doi/abs/10.1002/adfm.201706815
Dahiya, A.S., Sporea R.A., Poulin-Vittrant, G., and Alquier, D.
Stability evaluation of ZnO nanosheet based source-gated transistors, Nature, Scientific Reports, Article number 2979, February 27, 2019. https://www.nature.com/articles/s41598-019-39833-8
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