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And Then, There Were Three

How long can the silicon foundry sector continue to adapt, as physical limits make further shrinkage virtually impossible?
  1. Introduction
  2. Foundries at the Forefront
  3. Shakeout
  4. A Bright Future?
  5. Author
semiconductor fabrication equipment

Relentless year-over-year improvements in integrated circuits don’t come cheap. For years, these advances have been boosted in part by silicon foundries that invest in new technology by aggregating demand from design companies that don’t have factories of their own. As of last summer, however, only one such “pure-play” foundry continues to pursue the latest silicon generation, along with two companies that also make their own chips. The dwindling of suppliers revives the longstanding question of how the industry can adapt as physical limits eventually make further shrinkage impossible (or impossibly expensive).

Still, the story sounds familiar. “Every time people say Moore’s Law has finally hit the wall, people come up with new, innovative approaches to get around it,” said Willy Shih, Robert and Jane Cizik Professor of Management Practice at Harvard Business School.

The silicon industry has tracked the 1965 observation by Gordon Moore, co-founder and later head of Intel, that transistor counts were doubling every year (later changed to every two years). This exponential growth became enshrined as a “law,” which became a collective self-fulfilling prophesy as companies feared losing business if they fell behind its aggressive schedule. Successive generations were labelled by an ever-shrinking distance, currently 7nm, although this designation long ago lost any clear relationship to the transistor’s gate length or other features. In the 1990s, Moore’s Law became formalized in the National (after 1998, International) Technology Roadmap for Semiconductors, which spelled out what manufacturers, equipment suppliers, and academic researchers would need to do to keep the industry on track.

Unfortunately, exponentially increasing transistor counts were accompanied by corresponding increases in the costs to build fabrication plants and develop more aggressive processes and novel device structures. These costs, and the need to keep the expensive equipment in constant use, have long made it almost impossible for a smaller company to manufacture a novel chip design itself. “The capital investment to supply a growing market and to push leading-edge research can only be supported by a company that has a large revenue,” probably $30 billion a year or more, said Paolo Gargini. “It’s just a game for the big boys,” said Gargini, formerly at Intel, who has headed the formal roadmap through its recent rebirth as the International Roadmap for Devices and Systems (IRDS).

Nonetheless, when GlobalFoundries announced in August 2018 that it was halting development of its 7nm process, “it was quite a shocker for a lot of people,” Shih said. The foundry company had originally projected risk production—early manufacture with relaxed quality guarantees—of 7nm products in spring 2018, and until recently seemed committed. Now, the only remaining pure-play foundry developing leading-edge technology is Taiwan Semiconductor Manufacturing Company (TSMC), whose 7nm process has been in production since early 2018. Besides TSMC, Samsung, which has an important foundry business in addition to manufacturing its own chips, announced in fall 2018 that it was ready for risk production of 7nm. Intel, whose current 10nm process is often regarded as similar to TSMC’s 7nm process, devotes most of its attention to its own chips.

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Foundries at the Forefront

TSMC pioneered in 1987 the concept of a pure-play foundry. Before that, “If you had a new idea, you really didn’t have a place where you could test it” without paying for a dedicated factory, Gargini said. The advent of foundry capacity was “the best thing that could have happened for the industry,” he said. “The iPhone would never have existed if we didn’t have this model.”

At first, TSMC replicated older, less-profitable technologies and grew by “taking the rejects from the leading semiconductor companies.” Gargini said. However, “by 2000 or so they were within shooting range of the leading companies.”

Later foundries have mostly confined themselves to following the leaders, but GlobalFoundries seemed to have higher aspirations. The company was created in 2009 from the manufacturing operations of Intel’s arch-competitor Advanced Micro Devices (AMD). The company also acquired Singapore-based foundry Chartered Semiconductor, and in 2015 added the manufacturing operations of IBM.

Leading-edge semiconductor manufacturing is expensive and challenging, which is one reason AMD and IBM divested that part of their businesses. Into the 1990s, keeping up with Moore’s Law could mostly be achieved by “scaling,” following rules laid out by IBM’s Robert Dennard in 1974 to make better transistors by shrinking lateral dimensions, shrinking layer thicknesses, and increasing doping densities. Packing more transistors on the surface area of a wafer also offered benefits such as reduced cost per transistor, higher speed, and lower power dissipation.

Consolidation is “troubling” for U.S. semiconductor manufacturing, because “a vast amount of the world’s advanced foundry capacity is in TSMC’s hands.”

Continued exponential shrinkage brought transistors into collision with fundamental physical limits, though, such as gate oxides just a few atom-layers thick, as well as large leakage currents and other non-idealities in the tiny devices. To sidestep these limits, in the early 2000s manufacturers introduced multiple revolutionary innovations, such as high-dielectric-constant (high-k) gate dielectrics, metal gates, strained silicon, and the nonplanar transistors known as FinFETs.

More innovation will be needed, including in process technology. Especially challenging has been the lithography that prints the circuits, using progressively shorter ultraviolet wavelengths to create tinier features. This shrinkage stalled for years at a wavelength of 193 nm because the next huge jump, to extreme ultraviolet (EUV) at 13.5nm, requires different sources, optics, and exposure techniques. Instead, designers have exploited liquid immersion, multiple exposures, and other tricks to extend 193nm lithography. With the 7nm generation, EUV is finally being used for some processing levels, but economically viable throughput and yield won’t come easily.

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These challenges are not new, but the withdrawal of companies from the leading edge raises a “very valid question,” Shih said. “If there’s less competition, are we going to push the frontier less?” So far, there are still multiple suppliers.

“As long as you have two, it’s sufficient; if you have three it’s great,” Gargini said. “Samsung can do a lot of the stuff that TSMC can do,” and TSMC’s lead already meant that “there’s nothing that is so special that GlobalFoundries was doing,” Gargini said. AMD, for example, already made many of its most advanced central processing units (CPUs) and graphics processing units (GPUs) at TSMC.

Still, Shih notes that the consolidation is “troubling” for U.S. semiconductor manufacturing, because “a vast amount of the world’s advanced foundry capacity is in TSMC’s hands in three fabs in Taiwan.” He added that “People who worry about the defense-industrial base are very concerned about this issue.”

To be sure, GlobalFoundries and others (including TSMC) can still build very powerful products using older technologies. Moreover, Shih notes, “Some people say that, once we went below 14nm, or perhaps even higher like 22nm, the unit cost per transistor stopped decreasing and started increasing again.” As a result, “more and more users say ‘That [leading-edge] process is so expensive, I actually don’t need it,'” he said, unless they are “making things for cellphones or FPGAs or the bleeding-edge stuff like Intel micro-processors, where you really need the ultimate in performance and power.”

Indeed, a manufacturer that specializes in digital logic may not need a broad range of processes. In contrast, foundries support a whole range of devices, such as image sensors, and devices for analog, radio-frequency, and ultra-low-power circuits. Reliably implementing such mix-and-match processes in a design environment that lets multiple customers use them is often more important to designers than having the latest-generation technology. For example, although TSMC boasts dozens of high-end customers for its 7nm process, for example, it continues to support older-generation processes, even the 180nm technology it introduced 20 years ago, which is good enough for many customers.

If leading-edge development slows down, though, it might give other companies, including those in mainland China, more chance to compete. “The Chinese are having trouble at the leading edge, but they’re catching up on some of the trailing-edge technologies,” Shih said. “The thing that is driving TSMC is less competition from GlobalFoundries; it’s competition from Made in China 2025 [a Chinese program to improve domestic manufacturing competitiveness].”

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A Bright Future?

In the end, though, no amount of innovation can extend exponential scaling forever. Logic designers “are waiting for EUV to save the game,” Gargini said, but even if advanced lithography buys a few years, “that solution comes to an end.” In perhaps 2020 or 2021, he conjectured, “Samsung, TSMC, or Intel, one of them will make a big announcement that their next product is 3D [three-dimensional],” which would offer more transistors through vertical stacking. Memory manufacturers (including Samsung) have already begun to introduce 3D structures, both by stacking processed layers and growing multiple layers of devices (see “Electronics are Leaving the Plane,” Communications, August 2018). Memory has special advantages for 3D structures, such as uniform and redundant layouts, and low power (because most transistors are idle).

In contrast, in logic applications, many more transistors are active, and removing the heat they produce is enormously challenging even in the easier-to-cool planar layout. So far, logic companies are testing the 3D waters with advanced packaging techniques for GPUs and other high-performance products. “We still can squeeze another two or three generations out of 2D,” Gargini said, but he sees full 3D as inevitable and adding another 15 years of performance growth. “3D is not really as much of a revolution” or as risky as the process innovations the industry has already implemented, he said. “The big guys can do it anytime they decide to do it.”

The semiconductor industry faces challenges that we may look back on as the end of Moore’s Law. Nonetheless, there are continued opportunities for better products, and so far there are still foundry companies ready and able to enable new designs. “There is a bright future,” Gargini insists. “I think it’s a very good balance.”

*  Further Reading

International Roadmap for Devices and Systems 2017 Edition, IEEE,

Shih, W. C., Chien, C.F., Shih, C., and Chang, J.
The TSMC Way: Meeting Customer Needs at Taiwan Semiconductor Manufacturing Co., Harvard Business School Case Collection 610-003, August 2009,

Monroe, D.
Electronics are Leaving the Plane, Communications, August 2018,

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