A Versal Story in the Era of Hardware AI: Why the Chinese Could Win

Currently, a real “battle of the giants” is unfolding in the market for chips designed for use in real-time artificial intelligence systems. A separate “front line” in this confrontation is the development and implementation of SoM with Programmable Logic. This post is dedicated to one small “battle,” on the example of which we want to show why, in our opinion, China could win this “war.”

Since the announcement in 2019 by Xilinx (which then bore this name without a proud three-letter prefix), Versal ACAP (Adaptive Compute Acceleration Platform) chips were inaccessible to developers—the first development boards cost tens of thousands of U.S. dollars, and the difficulty of developing your own board for this chip would scare off anyone other than Tony Stark.

A lot of water flowed, and a lot of developers’ tears were shed, but a silicon Versal is just as unavailable as The Palace of Versailles: the cheapest kit from AMD–VEK280 is sold by the official suppliers for $7K, excluding delivery and customs clearance. The classic argument in the style of “if you don’t have money for an iron door, you don’t need it” does not always work in the field of R&D—a rare developer will refuse to study a top-end chip at the expense of his employer, but even with this approach, the cost is too high.

Of course, one can recall the SoM Kria version with Versal on board announced a couple of years ago was probably designed to solve the same problem as the already existing Kria K26—to make the price affordable and relieve printed circuit board designers from developing another 20-layer board.

The problem is that the announcement of AMD Xilinx has so far remained an announcement, but the developers from Alinx, the Chinese company, did not waste any time. This company already is known for its inexpensive development boards with Zynq‑7000 and Ultrascale+ on board, not much different from SoM. Now they not only promised, but also mass-produced the SoM V100 with the XCVE2302-SFVA784-1LP-E-S chip (Versal AI Edge family) for $750 [1].

Figure 1 – The VD100 kit is in good hands.
Credit: Maksim Popov

The main characteristics of SoM are impressive: RAM—4 GBytes DDR4 (64-bit data-bus), 64 MBytes QSPI FlashROM, 8 GBytes eMMC, Gen4 ×8 PCI-Express, 8 x GTY up to 12.5 Gbps, 53 (for ARM cores) + 106 (for FPGA part) input/output lines, two Samtec ADF6-40-03.5-L-4-2-A-TR connectors with 160 pins each. And at the same time, the single supply voltage 12V, and the dimensions are 65 x 60 mm. But the most important thing is the price, which is almost 10 (!!!) times lower than the American kit VEK280.

The good news doesn’t end there: there’s no need to wait for your own carrier board to be designed and manufactured—the VD100 kit includes one, so it’s ready to go straight out of the box. The carrier board implements PCIE 4.0, SFP+, Gigabit Ethernet, UART, MIPI, CAN, USB 2.0, I2C EEPROM, thermal sensor, RTC, etc. And the dimensions of the carrier board are only 182 x 107 mm.

So, now almost anyone can experience the beautiful Versal in every way (after buying a kind of an ultra-economy class “ticket” to a prestigious club, albeit for a small side chair at the back row).

Let’s be fair—a full-fledged “ticket” does not just cost $7K (VEK280), $12K (VPK120) or even $18K (VPK180) for nothing. Each of these kits from AMD not only has a more advanced chip compared to the Alinx V100, but also has larger RAM and a wider range of interface connectors.

However, Alinx has something to answer this challenge: the V100 is, first of all, a SoM, which makes it possible to integrate it into the final product using a much simpler custom carrier board with all the necessary connectors. Taking this into account, the Alinx “side chair” may first appear in the stalls and then, in the VIP box. But AMD’s kits, although full-featured and high-performance, are just evaluation boards that are not applicable in the final product. This means that the developer will have to become a “Superhero” in order to create the own board for the Versal chip from scratch. As they say, “Avengers, assemble!”

There is, of course, a fly in the V100 ointment. The developers from Alinx were so inspired by Kria that they also used “legendary” Samtec connectors “well-liked” by all designers and engineers. Who among us hasn’t drilled them from the side with the thinnest drill, forgetting to route that very necessary pin right in the middle in the inner row? However, to achieve the required transmission speeds with a compact size, there is hardly an alternative to Samtec connectors.

The authors have tested this SoM in their projects for too little time to know all its capabilities and shortcomings and make an unambiguous conclusion. But the fact that the Chinese manufacturer immediately provided full documentation in the language of Shakespeare and a repository with a large number of examples [2] tells us about the seriousness of their intentions. We can only hope that the quality of both the board and the code in the examples will be as brilliant as the Versailles’s.

It may seem that we are praising the VD100, but it is not so. We take a neutral position, advocating universal progress throughout the world. We just hope to spark discussion on the topic among the experts in this field and (perhaps) push AMD Xilinx towards a more flexible behavior strategy. After all, VD100 is still based on a chip from AMD Xilinx. But the fact that the place between the consumer and chip manufacturer is increasingly being occupied by the Chinese integrators hints that they are the ones making the technology more accessible to a wide range of developers, and they will rake in the profits. And in the near future, the development of their own solution looms; it will displace less flexible and efficient competitors—as happened so many other times in many areas.

So, we stock up on popcorn and watch the “battle of the giants.” Enjoy watching, everyone.

References

1. AMD Versal AI Edge Series Product Selection Guide. XMP464 (V1.10). AMD, 2024. 7 p.
2. Alinx VD100 Development Board Repository on Github: https://github.com/alinxalinx/VD100_2023.2.

Aleksandr Romanov (a.romanov@hse.ru) is an Associate Professor and Head of CAD Laboratory at HSE University, Moscow, Russia. Profile: https://www.webofscience.com/wos/author/record/444344

Maksim Popov (maks@bigprinter.ru) is a Senior Software Specialist and Head of R&D Department in Bigprinter Digital Innovations, LLC