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Driving an Innovation Contest into Crisis

Aleksandr Romanov considers how a lack of permanent leadership is impacting the InnovateFPGA contest.

Aleksandr Romanov, associate professor of HSE University June 1, 2022

On June 23, 2022, the Grand Final of one of the key international FPGA design contests——was held in San Jose, CA. Writing on the eve of this important event, I would like to share my views on this contest: What it was, what it has become, and why the crisis has happened.

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A longtime fan of this contest, I participated in it for many years (first as a student, then as a supervising professor of student teams, and even as a member of the judging committee). I constantly track its results, collect interesting materials, and follow the development of the contest.

In due time, this contest was almost the only way for students and graduate students from developing countries to get their own Terasic development board with an Altera chip. The point is that Terasic donated a development board worth about $200 (!) to the participants of the competition who submitted their projects and were able to describe its Technical Proposal at a sufficient level within the set time limit. I can share my own experience: for three to four years of participating in these competitions and other activities in the Altera Education Program, I collected enough development boards so that I could create my own electronics group and started introducing FPGA learning into the educational process, the results of which did not force me to wait for a long time, were noticed by the university administration and embodied in a full-fledged research and design laboratory, through which hundreds of students, studying on hundreds of different development boards with FPGA and other equipment, pass every year. And it all started with a mere student project!

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What the Contest Is

The advantages of the contest were always its fairly transparent and understandable rules, adequate deadlines for passing the stages, and honest review of works.

Usually, a competition was announced in the fall, registration opened on the competition website, and participants could submit their Technical Proposal within a month. Those who met the requirements advanced to the semifinals and were sent boards and possibly additional expansion boards. Getting to this stage was already a major achievement because the judging was strict.

After the teams received the boards, they had four to five months to develop their project and submit the technical paper. Then, several dozen projects were selected for the Regional Final. It was not easy to get there but it was possible, if the project was well developed and adequately presented. In principle, at this stage, the project description was already suitable as a draft for submitting an article to a scientific journal.

Next, the teams had to finalize the draft within a month based on the discussion in open comments and comments sent from the judging committee; it was necessary to submit Demonstration, as well as publicly shared Project source code.

As a result, finalists received awards with certificates, cash prizes, medals, and FPGA boards; Gold award teams went to the Grand Final (usually 1–3 finalists).

Now the competition is divided into Americas, APJ, EMEA, and Greater China regions. The Grand Final was held among the finalists from all regions.

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The Russians at InnovateFPGA

Russian teams were always well represented in the European section of the competition and played a significant role there. Every year since 2010, I could see five or more projects from teams from post-Soviet countries. In 2018, in the regional competition in the EMEA section, post-Soviet teams took all top places. 2019 was even better, which is not surprising; of 61 participating teams, there were about 20 Russian-speaking teams (10 from HSE University).

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Contest Problems

In my opinion, the main problem of the InnovateFPGA contest is the lack of a permanent team to lead. As I understand it, this competition was not the main business for either Terasic or Altera in the past and is not the main business for (especially) Intel FPGA now.

From year to year, the site of the contest, the format and direction of the competition were constantly changing. Because of this, unfortunately, the results and reports on projects of previous years were lost. There were very interesting ideas and developments that could be used by both academic teams for educational purposes and small individual development teams, which would increase the popularity of this contest and the development of digital design in general. It is difficult for new participants to enter the competition because they cannot draw on previous experience and see what the finalist projects were like. This circumstance does not contribute to an increase in the average level of projects and also, obviously, gives an advantage to those participating in the contest every year.

The contest was not held in some years, and its announcement came as a surprise. It was advertised in an unsystematic way. A permanent community was not formed around the contest, only its big fans such as me remembered it.

It was only a period of relative stability (from 2015 to 2019), when the competitions were held every year, and the requirements and format did not change much, that made it possible to rectify the situation somewhat, and the number of participants and the quality of projects began to grow.

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COVID-19 and the “Green” Agenda

Then came the crisis caused by the restrictions due to COVID-19. Everything closed, and we were left without InnovateFPGA for two years. Although I actively campaigned for students and prepared them for participation in the competition, there was still no announcement, and fellow organizers did not respond to letters.

Finally, at the end of the summer of 2021, the long-awaited announcement came! An updated site, new partners in the face of Microsoft, and … complete disappointment and misunderstanding.

This is what was written in the contest announcement: “… The InnovateFPGA Design Contest seeks to explore solutions that reduce environmental impact and the demand that we place on the planet’s resources.” Also, among the requirements, it said: “Contestants will utilize the Terasic DE10-Nano FPGA Cloud Connectivity Kit, with Analog Devices plug-in cards, and connected to the cloud using selected Microsoft Azure Cloud Services.”

That is, participants were placed in a rather narrow framework of projects, with the help of which it was necessary to urgently save the planet and at the same time be sure to use Microsoft Azure Cloud Services. Such a combination cut off a huge number of options for purely engineering projects, reducing everything to agricultural topics and even requiring developers to have knowledge of processing big data using such a powerful, but rather specific, tool as Microsoft Azure.

As a result, there was a significant reduction in the number of participants. There were formally 41 applications in the EMEA section, but approximately 30 were actually filled in. Pretty similar topics, mainly devoted to ecology and, of course, COVID-19.

It was fun to follow the interesting project “Jaguar” (, representing the TinyML Neural Network accelerator for CPU. The developers of “Jaguar” tried to attach the project to the subject of the contest’s theme by the fact that “reducing the power consumption of AI chips will reduce the world’s CO2 emissions.” Naturally, such a project did not go beyond the Semi Final.

The requirement to use Microsoft Azure was just as formally fulfilled. In many projects, some developers decided to just forget about it, while others used it as just cloud data storage, maximum for visualization. Only a few projects utilized the full power of Microsoft Azure tools for analyzing and processing data, as well as Azure IoT.

The overall quality of projects also declined significantly. Even among the finalists in the EMEA section, in my opinion, only the project “A smart underwater microbial delivery system for coral reef habitat recovery” ( deserved attention. (The other two submissions clearly fall short of its level.) For example, the project “smart farm system” (—both in presentation and content, looks like the untidy product of a first-year student. Another project, “CO2 gas sensor for air quality monitoring” (, is much better, but I still did not understand where Azure was used.

In other sections, the situation is approximately the same.

The overall activity of the participants also decreased; there is practically no discussion in the comments to the projects. I was very unpleasantly surprised by the negligence of the moderators regarding spam links to resources unrelated to the contest.

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Thus, I have to admit the once-good contest (potentially the most powerful tool capable of promoting Intel FPGA and Terasic technologies and products) for engineers and students who are fond of FPGAs, is experiencing a crisis due to the lack of proper attention to its promotion and financing, as well as incorrect strategies for requiring participants to follow boring mainstream topics and use a limited set of tools.

I would like to hope the emergence of this negative trend will be noticed by the organizers, and next year, the necessary and positive changes will take place.


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