For 50 years, semiconductor chips have been essentially fat devices, with transistors laid down in greater and greater densities. The way to keep riding Moore’s Law was to make transistors ever smaller and closer together in a plane. Now, such miniaturization has been slowed by the difficulty of managing power consumption and heat, and by the soaring cost of manufacturing.
Chips are made by projecting a circuit design onto a fat silicon surface, then using a photochemical process to etch the circuits into the silicon. But as the circuit features get smaller and smaller, they begin to “leak” current, which wastes power and produces heat. Although no one knows just where the limit lies, it seems likely the shrinkage of conventional silicon transistors will eventually end.
The industry’s answer to the power and cost problems has become 3D, building electronic devices upward as well as outward. The principle is simple and even obvious, but reliable and affordable manufacturing remains difficult. Many variations on the 3D theme have emerged, but there are three basic approaches, sometimes referred to as 3D packaging, 3D integration, and monolithic integration.
Although now in limited production, 3D chips and packages of various types will become common in the market over the next 10 years, says Simon Wong, a professor of electrical engineering at Stanford University who specializes in integrated circuits. “I believe Moore’s Law will continue for many more generations, as there are innovative ideas for scaling devices and mediating power dissipation,” Wong says. “However, the escalating manufacturing cost is an issue. 3D allows continuous improvement in performance and reduction of power dissipation at each technology node, extending the lifespan of each node beyond three years, and allowing manufacturers more time to recover the huge capital investments.
“Instead of continuing to shrink the transistor, one can design a system in the third dimension for similar levels of performance improvement,” Wong says. 3D chips will find application virtually everywhere but will be especially attractive in mobile devices, where space is limited.
The oldest and simplest 3D packaging method is to put two chips face-to-face, called “flip chips,” and join them by solder “bumps.” A more advanced idea, for joining multiple chips, is to stack conventional 2D chips in a number of layers, and bond and connect them electrically around the edges. The approach is relatively inexpensive and uses conventional semiconductor methods. But the resulting devices are bulky—which is not ideal for the smallest mobile devices—and relatively slow because signals have to travel across and around the chip layers. Consumer flash memory is now routinely built by this type of stacking.
Stacking Chips
Tighter integration can be achieved by a newer technique called through silicon via (TSV), in which wires or “vias” extend vertically through the chip stack and connect to the outside. Instead of lengths measured in millimeters, the vias are just tens of microns long and chip interconnects can be much denser.
A number of TSV devices are now in production. Samsung, for example, has introduced a TSV-based 8GB dual inline memory module (DIMM) that it says increases the density of transistors by 50% and reduces power use by as much as 40% compared to similar 2D DIMM chips. Also, IBM and Micron Technology in December announced a 3D Hybrid Memory Cube using TSVs that the companies said will work 15 times faster than today’s technology, for high-performance computing architectures, in a 90% smaller package.
The most common approach today to building TSV devices is to stack individual dies, or chips. That approach enables the testing of each before assembly.
A more advanced method stacks whole wafers, then dices them into individual chip stacks. Although that simplifies fabrication, the problem is that if a single layer is bad, the entire chip stack must be discarded, so yields are relatively low at present. Tezzaron Semiconductor, for example, divides circuitry into sections that are built on separate wafers, with hundreds of thousands of vertical connectors built into them. Finished wafers are metalized and then aligned with a precision of 0.5 micron, bonded, and diced into individual chip stacks.
3D chips will find application virtually everywhere but will be especially attractive in mobile devices.
Subramanian Iyer, an IBM Fellow with the company’s microelectronics division, says wafer stacking makes sense with a product such as memory with many redundant cells. He says it is possible wafer stacking may become more widespread when processors have many cores and can afford to forfeit a small number of them. Like so many things in the chip business, it is ultimately a question of economics.
Meanwhile, IBM and others continue to advance an idea born in the 1970s, in which chips are mounted facedown, side by side, on an “interposer,” originally ceramic but now silicon. While the chips lie in a plane, TSV wires extend vertically short distances down into the silicon, connect in various ways, and then come back up. Because the wires are very short and the chips are very close, the whole device is capable of great bandwidth. A three-chip device, consisting of an analogue-digital converter, a digital signal processor, and silicon germanium transceivers, built last year by IBM and Sematech, can communicate between chips at up to 2 Tbits per second, Iyer says.
The relative shortness of the interconnects in this IBM device, and in 3D structures generally, accounts for the favorable power dissipation characteristics, according to Iyer. He says that in a multi-chip system about 30% of the power goes to communicating over wires, and at the chip level that jumps to 80%. The longer the wires, the more heat is produced.
“What 3D does is greatly shorten the wires by bringing components closer to each other,” Iyer says. “The 3D part of this is independent of transistor scaling.”
Because all of these methods are essentially vertical stacks of 2D devices, they are often called 2.5D. True 3D, in the view of some, requires a single, monolithic integrated circuit. In these, devices are built on top of interconnects using integrated circuit fabrication technology, rather than stacking chips or wafers and connecting them with TSVs.
The advantage of monolithic integrated circuits is that the interconnects are much denser than they are with TSVs because the area needed to make a connection, in the order of 60 nanometers, is about 100 times smaller, says Stanford’s Wong. Samsung and MonolithIC 3D, for example, have built very high-density 3D monolithic memories.
But monolithic 3D technology is in its infancy. A layer of transistors is made, they are connected by wires, then another layer of transistors is put down, and so on upward. The biggest problem is that the processing of subsequent layers is so hot—above 400 Celsius—that it can melt the wires below. That presently limits the number of layers to just two or three, Wong says.
Wong and colleagues at Stanford have built a monolithic 3D field-programmable gate array (FPGA). The monolithic 3D FPGA is built in a single complementary metaloxidesemiconductor (CMOS) wafer, but has two layers. Wong’s initial FGPA had a second layer of nonvolatile resistive RAM, or RRAM, which does not use transistors, but he is now working on a FGPA that has a second layer of transistors followed by a third layer of RRAM.
Monolithic integrated circuits show their strength with complex devices and dense interconnects.
Monolithic integrated circuits are a good way to make such hybrid chips, using materials that are higher performing than CMOS, Wong says. “You can imagine,” he says, “integrating indium phosphide or gallium arsenide on top of silicon.”
Stacking of 2D chips is the best method when the designer has many layers of relatively simple, uniform devices, like memories. Monolithic, on the other hand, shows its strength with complex devices and dense interconnects.
“Stacking of flash chips only requires vertical connections at the pads, and hence can be easily supported by 3D packaging,” Wong says. “But the FPGA that we have demonstrated requires dense device-dimension vertical interconnects that cannot be supported by TSV.”
Abbas El Gamal, a professor of electrical engineering at Stanford, says it is possible the future may hold a combination of 3D CMOS chips and some entirely new nanotechnology. “Maybe we’ll have different kinds of transistors, not just smaller ones,” El Gamal says.
Perhaps so. But today the consensus is that we do need to exploit the third dimension, and that ability is increasingly appearing in semiconductor-based products.
Further Reading
Friedman, E.
3D design: Architectures, methodologies, and test circuits, D43D: 2nd Design for 3D Silicon Integration Workshop, Lausanne, Switzerland, May 2628, 2010.
Garrou, P., Lu, J.J.-Q., and Ramm, P.
Three-Dimensional Integration, Handbook of Wafer Bonding, Wiley-VCH Verlag & Co., Weinheim, Germany, 2012.
Liauw, Y., Zhang, Z., Kim, W., El Gamal, A., and Wong, S.
Nonvolatile 3D-FPGA with monolithically stacked RRAM-based configuration memory, 2012 IEEE International Solid-State Circuits Conference Digest of Technical Papers, San Francisco, CA, Feb. 19-23, 2012.
Maly, W., et al.
Twin gate, vertical slit FET for highly periodic layout and 3D integration, Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and Systems, Gilwice, Poland, June 16-18, 2011.
Wong, S. and El Gamal, A.
The prospect of 3D-IC, IEEE Custom Integrated Circuits Conference, San Jose, CA, Sept. 1316, 2009.
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