InnovateFPGA: Wrong Strategy Drives One of the Best FPGA Development Contests into Crisis

On June 23, 2022, the Grand Final of one of the key international FPGA design contests–InnovateFPGA–will be held in San Jose, CA. On the eve of this important event, I would like to share my views on this contest: what it was, what it has become, and why the crisis has happened.

Introduction

А longtime fan of this contest, I participated in it for many years (first as a student, then as a supervising professor of student teams, and even as a member of the judge committee). I constantly track its results, collect interesting materials, and follow the development of the contest. 

In due time, this contest was almost the only way for students and graduate students from developing countries to get their own Terasic development board with an Altera chip (now Intel FPGA). The point is that Terasic donated a De1-SoC/De10-nano development board worth about $200 (!) to the participants of the competition who submitted their projects and were able to describe their Technical Proposals at a sufficient level within the set time limit. (In 2019, it was even a Starter Platform for OpenVINO™ Toolkit worth about $500 (!).) For a student interested in digital design, this is very useful equipment. I can share my own experience: for 3–4 years of participating in these competitions and other activities in the Altera Education Program, I collected enough development boards so that (already as a young teacher) I could create my own electronics group and started introducing FPGA learning into the educational process, the results of which did not force me wait for a long time, were noticed by the university administration and embodied in a full-fledged research and design laboratory, through which hundreds of students, studying on hundreds of different development boards with FPGA and other equipment, pass every year. And it all started with a mere student project!

What the contest is

The advantage of the contest was always fairly transparent and understandable rules, adequate deadlines for passing the stages, and honest review of works.

Usually, a competition was announced in the fall, registration opened on the competition website, and participants could submit their Technical Proposal (high-level project introduction and performance expectation, block diagram, expected sustainability results, projected resource savings) within a month. At this stage, empty projects and those that did not fit the theme of the competition were eliminated. Those who met the requirements advanced to the semi-finals and were sent boards, and possibly additional expansion boards. Getting to this stage was already a major achievement because the judging was strict. Here, of course, everything was not always smooth: for example, in 2015, one of my teams waited for a De1-SoC board for almost 6 months, while for some reason it came from Taiwan to a professor in Germany, lay there for several months, and only after through a chain of several contest managers, we were able to find it. Of course, there was no question of any continuation of participation in the competition that year, but then we did not count on much–the main task was to receive an advanced FPGA board for that time, which was very useful for our internal projects.

After the teams received the boards, they had 4–5 months to develop their projects and submit the technical paper (high-level project introduction and performance expectation; block diagram; FPGA virtues demonstrated by project; functional description and implementation; performance metrics; sustainability results, resource savings achieved; conclusions). At this stage, another panel of judges selected several dozen projects among the teams that made it to the Regional Final. It was not easy to get there, but it was also possible, if the project was well developed and adequately presented. In principle, at this stage, the project description was already suitable as a draft for submitting an article to a scientific journal or to proceedings of the intermediate-level scientific conference, which many teams used, "killing two birds with one stone".

Next, the teams had to finalize the draft within a month based on the discussion in open comments on the draft and comments sent from the judge committee; it was necessary to submit Demonstration (Video demonstration; Description of theory, function, and performance of design), as well as publicly shared Project source code.

As a result, the teams received Gold/Silver/Bronze/Iron/ excellence awards with certificates, cash prizes, medals, and FPGA boards; Gold award teams went to the Grand Final (usually 1-3 finalists).

It should be noted that the competition was originally divided into the European division (InnovateEurope) and the Asian division (InnovateAsia), which even had separate sites. Now the competition is united on one platform and divided into Americas, APJ, EMEA, and Greater China regions. I followed the European Region (EMEA) and USA the most. The Grand Final was held among the finalists from all regions.

The Russians at InnovateFPGA

Russian teams were always well-represented in the European section of the competition and played a significant role there. Every year since 2010, I could see 5 or more projects from teams from Russia, Ukraine, Belarus, and other Post-Soviet countries. The apogee of the participation of Russian teams in InnovateFPGA was 2018 and 2019.

In 2018, in the regional competition, Russian teams took 1 (Gold) and 2 (Silver) places, and a team from Ukraine – 3 (Bronze).

In 2019, 1 (Gold), 2 (Silver), and 3 (Bronze) places were won by Russian teams, which is not surprising: in the EMEA section, out of 61 participating teams, there were about 20 Russian-speaking teams (10 – from HSE University).

Contest problems

In my opinion, the main problem of the InnovateFPGA contest is the lack of a permanent team to lead. Since, as I understand it, this competition was not the main business for either Terasic or Altera in the past and is not the main business for (especially) Intel FPGA now. Its implementation largely depends on the size of the team that hosts it and funding, respectively. From communication with the organizers, this is very noticeable. In some years, it was carried out by employees of various Terasic divisions, clearly combining this work with the main one. From year to year, the site of the contest, the format and direction of the competition were constantly changing. Because of this, unfortunately, the results and reports on projects of previous years were lost. There were very interesting ideas and developments that could be used by both academic teams for educational purposes and small individual development teams, which would increase the popularity of this contest and the development of digital design in general. It is difficult for new participants to enter the competition because they cannot draw on previous experience and see what the finalist projects were like. This circumstance does not contribute to an increase in the average level of projects and also obviously gives an advantage to those participating in the contest every year.

Due to funding problems, the contest was not held at all in some years, and its announcement came as a surprise. The contest was advertised in an unsystematic way: i.e., teams, for example, could not prepare for the contest in advance, and its subject matter was not always clear. A permanent community was not formed around the contest, only its big fans like me remembered about it.

And only a period of relative stability (from 2015 to 2019), when the competitions were held every year, and the requirements and format did not change much, made it possible to rectify the situation somewhat, and the number of participants and the quality of projects began to grow.

Covid-19 and the new "green" agenda

The crisis caused by the restrictions due to Covid-19 came. Everything closed, and we were left without InnovateFPGA for two years. Although I actively campaigned for students and prepared them for participation in the competition, there was still no announcement, and fellow organizers did not respond to letters.

Finally, at the end of the summer of 2021, the long-awaited announcement came! Updated site, new partners in the face of Microsoft, and… complete disappointment and misunderstanding.

This is what was written in the contest announcement: "Demand for computing power continues to explode. The InnovateFPGA Design Contest seeks to explore solutions that reduces environmental impact and the demand that we place on the planet's resources. Today, we are applying our resources to deliver on bold goals. And we're not doing it alone: We invite teams to develop solutions that will have a real-world impact based on Intel Edge-centric FPGA."

Also, among the requirements there was: "Contestants will utilize the Terasic DE10-Nano FPGA Cloud Connectivity Kit, with Analog Devices plug-in cards, and connected to the cloud using selected Microsoft Azure Cloud Services."

Participants were placed in a rather narrow framework of projects, with the help of which it was necessary to urgently save the planet and at the same time be sure to use Microsoft Azure Cloud Services. Such a combination cut off a huge number of options for purely engineering projects, reducing everything to agricultural topics and even requiring developers to have knowledge of processing big data using such a powerful, but rather specific tool as Microsoft Azure. In addition, as some participants of the competition noted, trial access to Azure was provided for only 1 month.

As a result, there was a significant reduction in the number of participants. There were formally 41 applications in the EMEA section, but about 30 were actually filled in. Pretty similar topics, mainly devoted to ecology and, of course, Covid-19. 

It was fun to follow an interesting project "Jaguar," representing the TinyML Neural Network accelerator for CPU. The developers of "Jaguar" tried to attract the project to the subject of the theme contest by the fact that "reducing the power consumption of AI chips will reduce the world's CO₂ emissions." Naturally, such a project did not go beyond the Semi Final.

The requirement to use Microsoft Azure was just as formally fulfilled. In many projects, the developers decided to just forget about it, while others used it almost as just cloud data storage, maximum for visualization. The implementation of heavy calculations (like neural networks) was usually carried out on the FPGA, and not by the means which the organizers of the competition counted on, and only a few projects really used the full power of Microsoft Azure tools for analyzing and processing data, as well as Azure IoT.

The overall quality of projects also declined significantly. Even among the finalists in the EMEA section, in my opinion, only the project "A smart underwater microbial delivery system for coral reef habitat recovery" deserved attention. (The other two clearly fall short of its level.) For example, "smart farm system"–both in presentation and content–looks like an untidy craft of a first year student. Another project – "CO₂ gas sensor for air quality monitoring"  – is much better, but I still did not understand where Azure was used.

In other sections, the situation is approximately the same.

The overall activity of the participants also decreased; there is practically no discussion in the comments to the projects, except for the same type of comments from the same account with congratulations on reaching the final.

It can be said that there were no Russian projects this year, but I was very unpleasantly surprised by the negligence of the moderators who allowed several projects from Ukraine to use the contest platform for unworthy political statements and posting spam links to resources unrelated to the contest.

Conclusions

Thus, I have to admit that the once-good contest (being potentially the most powerful tool capable of promoting Intel FPGA and Terasic technologies and products) for engineers and students, who are fond of FPGAs, is experiencing a crisis due to the lack of proper attention to its promotion and financing, as well as wrong strategies for forcing participants to follow boring mainstream topics and use a limited set of tools. At the same time, indulgence in ugly political antics at an engineering competition contest goes beyond the threshold of permissible.

I would like to hope that the emerging bad trend will be noticed by the organizers, and next year the necessary and positive changes will take place.

 

Aleksandr Romanov (a.romanov@hse.ru) is an Associate Professor and Head of CAD Laboratory of HSE University, Moscow, Russia. Profile: https://publons.com/researcher/3696120/aleksandr-romanov/