The foundation of high-performance computing (HPC) is undergoing a revolution, with the introduction of add-on accelerators such as graphic processing units, Intel's MIC chip, and field-programmable gate arrays, writes Michael Feldman. However, he says an emerging variant of this heterogeneous computing approach could replace the current accelerator model in the near future.
ARM recently announced its big.LITTLE design, a chip architecture that integrates large, performant ARM cores with small, power-efficient ones. This approach aims to minimize the power draw in order to extend the battery life of mobile devices.
The big core/little core model was developed by researchers at the University of California, San Diego (UCSD) and Hewlett-Packard Labs in 2003. "The key insight was that even if you map an application to a little core, it's not going to perform much worse than running it on a big core," says UCSD researcher Rakesh Kumar. The big/little model has both types of cores on the same die and it consolidates on a homogeneous instruction set.
Feldman says assigning tasks to cores would be more static for HPC, because maximizing throughput is the overall goal. The most likely architectures to adopt the big/little model are x86 and ARM.
From HPC Wire
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