Nanoscale Makes a Power Play

In the relentless pursuit of more powerful and energy-efficient transistors, researchers continue to explore ways to take performance to a higher level. One method that has captured their attention is the use of nanoscale transistors. These devices, which typically measure between 1 nm (one billionth of a meter) and 10 nm in gate length, are likely to play a prominent role in the future of computing and electronics.

Yet building nanoscale transistors presents a basic problem. They are bound by physical constraints that limit how efficiently circuits can turn on and off. This effect—referred to as the Boltzmann tyranny—makes it extraordinarily difficult to optimize performance and energy consumption.

“Moore’s Law has allowed engineers to design MOSFETs [Metal-Oxide Semiconductor Field-Effect Transistors] that are smaller and smaller. But we’ve reached a point where it’s nearly impossible to reduce the voltage further, which means you can’t dramatically reduce power consumption,” said Gerhard Klimeck, a professor of electrical and computer engineering at Purdue University.

The repercussions are jarring. This barrier makes it more difficult to push CPU speeds higher, reduce energy and cooling costs in datacenters, and build more efficient Internet of Things (IoT) devices. While methods such as 3D chip stacking, chiplet architectures, and specialized accelerators offer workarounds, these architectures don’t address the fundamental limitation problem.

Down to the Wire

Researchers at the Massachusetts Institute of Technology (MIT) believe they have finally discovered a viable solution. In November 2024, they announced the development of innovative nanoscale 3D transistors that utilize ultrathin semiconductor materials. These transistors have vertical nanowires only a few nanometers wide and leverage quantum mechanical properties, rather than conventional electron flow, to achieve ultra-high performance along with low-voltage operation. The novel design takes advantage of quantum tunneling, a process by which electrons pass through energy barriers rather than having to go over them.

It’s akin to rolling a ball over a hill. The higher and steeper the hill, the more energy that’s required to get the ball over the top and to the other side. However, using quantum tunneling, it’s as if the ball can simply pass through the hill and wind up on the other side.

This advancement, which taps gallium antimonide and indium arsenide, addresses the limitations of traditional silicon-based transistors and the Boltzmann tyranny. In the future, it could complement or replace silicon transistors in datacenters and in various types of electronic devices, including smartphones and consumer electronics. In practical terms, these transistors could minimize the energy consumption per computation, or permit more computations with the identical computing energy.

“Transistors are the smallest unit in any modern microprocessor,” said Yanjie Shao, an MIT postdoctoral researcher and lead author of a paper on the topic that appeared in the journal Nature Electronics. “Ultra-scaled transistors that operate on quantum-mechanical tunneling could achieve steep turn-on slope, high drive current, and ultimate footprint scaling simultaneously. In future devices, this could lead to extreme energy efficiency without compromising performance,” he noted.

The project combined three core innovations. First, the team used quantum-mechanical tunneling as the fundamental operating mechanism. This engineering method differs from conventional silicon transistors and enables a sharper turn-on slope. Using tunneling, it’s possible to operate at 0.3 volts rather than 0.7 to 0.9 volts in the most advanced silicon transistors.

Second, the team used novel materials—a gallium antimonide/indium arsenide heterostructure—to replace silicon. “We are able to engineer the band alignment in the GaSb/InAs heterostructure to be most favorable for a high tunneling current,” Shao explained.

Finally, researchers developed an advanced nano-fabrication technology that permits narrow 3D vertical nanowires with diameters as low as 5 nanometers. This extreme miniaturization, combined with quantum confinement, yields both high performance and steep switching slopes. The vertical design is also significant because it replicates modern transistor architectures. This makes the technology attractive commercially.

Understanding the physics behind these transistors was critical. Ju Li, the Tokyo Electric Power Company Professor in Nuclear Engineering and professor of materials science and engineering at MIT, conducted first-principles modeling. Later, a research group led by David Esseni, a professor at the University of Udine in Italy, built a quantum transport simulation model.

As Klimeck (who was not involved in the project) noted, “Researchers in this space have been stuck for the past 20 years, and many have given up on developing advanced nanowire transistors. This is an important breakthrough that could change the industry.”

Meeting the Resistance

While the MIT group’s breakthrough is remarkable and it could have a profound impact on future transistor designs, commercial development remains over the horizon. “There is still a long way to go for this technology to be used in commercial production,” Shao said.

One obstacle involves device-to-device variations, and the precision required to build a specific nanoscale transistor. “Even a single nanometer matters a lot,” Shao explained. A bigger challenge is adapting current chip fabrication processes, Klimeck said. “This represents not just a technical shift but a massive manufacturing overhaul,” he added. “It’s like a Kosher kitchen; there are things you don’t mix. Gallium and indium are contaminants that are incompatible with silicon on the same fabrication line.”

In other words, the transition to manufacturing methods that support gallium/indium will likely be costly and time-consuming. One potential workaround would be to incorporate the technology into chiplets, Klimeck noted. These designs could support specialized applications where power efficiency is critical, such as IoT devices like doorbell cameras and industrial monitoring sensors.

Nevertheless, nanoscale tunneling appears to offer an on-ramp to a post-CMOS world. And MIT researchers aren’t alone in the quest for new and better transistors. A group at the University of Nebraska is also exploring materials and designs that could reshape the field. While other miniaturization approaches like photonics and carbon nanotubes have largely stalled out, the future of nanoscale transistors looks bright.

For now, the MIT group is continuing to refine transistor designs. One approach involves stacking vertical nano-fin configurations to improve uniformity across devices and simplify large-scale manufacturing. They’re also working to improve p-type tunneling transistors to match the performance of their n-type counterparts. This would create a complementary technology to serve as the backbone for faster and more energy-efficient circuits.

“Nanoscale tunneling transistors could be scaled to a very small footprint, smaller than likely any transistors demonstrated to date,” said the Nature Electronics paper’s senior author, Jesús del Alamo, the Donner Professor of Engineering in the MIT Department of Electrical Engineering and Computer Science. “They have the potential to further minimize computation energy for future AI and high-performance computing.”

Samuel Greengard is an author and journalist based in West Linn, OR, USA.