To address the problem of shrinking transistor geometries, researchers at the University of Illinois and the University of California, San Diego are developing stochastic processors. The processors are intentionally under-designed to be naturally error-prone under both normal and distressed conditions, with error tolerance supplied by either hardware or software. The underlying justification is that the looser architecture will make mass production of the processors much less expensive and simpler, while the easing of voltage scaling and clock-frequency strictures can yield substantial energy efficiency and performance gains.
The stochastic research group has devised a processor that allows for a 1 percent to 4 percent error rate, which can save between 25 percent to 40 percent on power in comparison to the default design. "Our vision is that all the errors that are produced get tolerated by the software," as software-based error tolerance provides greater flexibility, says Illinois computer scientist Rakesh Kumar.
From HPC Wire
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