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High, Not Flat: Nanowires for a New Chip Architecture


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scheme of silicon wafer with verticle transistors

Scheme of a silicon wafer with novel vertical transistors made out of silicon nanowires (without the upper p-contact).

Credit: Sander Mnster

Researchers from the Max Planck Institute of Microstructure Physics and the Forschungszentrum Dresden-Rossendorf have described the electrical resistance and current flow inside silicon nanowires. Their research could lead to a three-dimensional transistor architecture based on nanometer-sized wires.

Unlike current transistors, which are arranged lying flat next to each other and are about 50 nanometers in length, the new architecture, in which the transistors are rotated 90 degrees so they stand like tiny columns, would allow for numerous vertical transistors to be built on the area normally occupied by one flat transistor.

Nanowire-based electronics would be smaller and more energy-efficient, according to the researchers, and could enable the fabrication of extremely efficient solar cells.

From Forschungszentrum Dresden-Rossendorf (Germany)
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Abstracts Copyright © 2010 Information Inc., Bethesda, Maryland, USA


 

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