South Korean chipmaker Samsung Electronics aims to be first to adopt a new form of transistor that should allow Moore's Law to continue for another decade when it puts into production its 3nm semiconductor process toward the end of 2022.
It is just over a decade since the last major change to transistor structure went into production. The fin field-effect transistor (FinFET) emerged when the planar transistor structure that had served the industry well for several decades hit a physical limit. The problem lay in the relatively simple structure of the transistor's gate, an electrode laid over a thin channel between the source and drain that acts as an electrostatic valve. The gate's electric field, generated when a voltage is applied to it, controls whether electrons can pass through the channel, determining whether the transistor is switched on or not.
By the mid-2000s, chipmakers had succeeded in going beyond some expectations set by Moore's Law for the length of the gate. The 65nm node featured gates as short as 30nm that could switch quickly but suffered from high leakage. Charge carriers not only tunneled easily through the supposedly insulated gate, electric field lines generated from the drain were reaching the source region. That caused current to flow even when the transistor was supposed to be completely off. For several generations, gate length scaling stalled, to the point where chipmakers risked running out of space to place the conductive contacts needed to wire transistors to each other.
Beginning with the 22nm node, chipmakers switched to the FinFET. By lifting the transistor channel above the surface of the silicon, the gate electrode could be wrapped around three of its sides, instead of simply covering just the top surface, resulting in greater electrostatic control over electron flow. Now, even FinFETs are suffering issues similar to those of planar transistors a decade earlier. Surrounding the gate only on three sides still leaves an opportunity for some channel leakage to occur. The next step is to lift the channel above the silicon surface completely so the gate can wrap around the bottom as well.
While there are a number of possible gate all-around (GAA) structures, manufacturers like Samsung favor the nanosheet design, a structure proposed by CEA-Leti and IBM 15 years ago. It involves some steps that are challenging, but has the advantage of being able to reuse many of the steps used to build FinFETs. The result is not just one enclosed channel, but several stacked on top of each other: an approach that further improves the control exercised by a wraparound gate. In place of the original silicon fin, a sandwich of multiple silicon and silicon-germanium layers is grown. Silicon germanium is used as a sacrificial layer because it provides an easy target for a chemical etch that can dissolve those layers away, to be replaced by the gate materials.
The horizontal form factor of the nanosheet provides an easier way to tune the size of the transistor. A major issue with the FinFET is that in most cases, a single fin in a transistor rarely provides enough current to be useful in a circuit. Multiple fins have to be used in parallel, so the effective width moves up in comparatively large steps. In his presentation at the International Solid State Circuits Conference in February, Samsung vice president of design enablement Taejoong Song said his team has taken advantage of the ability to draw nanosheets with different widths to create denser and more reliable memory cells than is possible with FinFETs.
A further boost will come in the form of energy efficiency. Chipmakers will take advantage of the improved gate control to reduce the supply voltage. As active power consumption is proportional to the square of the supply voltage, the savings to be made here can be substantial.
The International Roadmap for Devices and Systems (IRDS), an organization that has tracked semiconductor technology for more than two decades and which provides pathfinding data for chipmakers, expects the few manufacturers still able to make leading-edge silicon to have transitioned to nanosheet structures by the middle of this decade. But they are not all moving at the same time.
Expecting initial production from its competing process by the end of this year, the world's largest semiconductor foundry, Taiwan Semiconductor Manufacturing Company (TSMC), has opted to stick with FinFETs for one more generation, claiming it can still deliver 70% better density compared to the preceding N5 or 5nm process. The Taiwanese company will move to nanosheets for the N2 or 2nm process that it hopes to debut by 2024.
Though the nanosheet brings benefits in terms of scaling, they will be far less dramatic than in the past. The IRDS estimates 12nm to be the limit for gate-length scaling for silicon-based transistors by 2030, a reduction of just 25% from what is achievable for 3nm nanosheet processes. There are also limits to how narrow they can become as well. Yet the IRDS still predicts an effective doubling in density according to Moore's Law to 2030 at least. The changes that allow scaling now have more to do with the way transistors are laid out and connected, rather than the dimensions of those devices.
For IRDS chairman Paolo Gargini, the changes the industry is making to achieve further scaling mark a return to what Gordon Moore said needed to take place during his keynote at the IEEE International Electron Devices Meeting (IEDM) held more than 45 years ago. "If you go back to the 1975 presentation, he said the largest contribution to scaling would be from what he called 'circuit and system cleverness,' and that is what we will be doing in the upcoming decade," Gargini says. In today's terms, Moore's prediction could be restated as "transistors will be evolving into clever topological 3D structures," he adds.
That stronger focus on transistor layout and interconnection has been building for some time. It is the main reason why the names of process nodes have become increasingly disconnected from physical dimensions on-chip. Whereas in the 1990s, the node name generally reflected metal half-pitch or the gate length, the moniker 3nm used by foundry suppliers Samsung and TSMC does not reflect any on-chip measurement. Even Intel's more conservative numbering of 5nm is still some way off from the actual gate length, which is at least three times longer.
Finding it difficult to reduce the spacing between parallel fins, chip-makers worked over the past decade to eliminate other sources of wasted space, such as how connections are made between transistors. Traditionally, the electrical connection to a gate would be placed to the side to avoid the risk of creating short-circuits with the source and drain connections. Intel found a chemical process that could reliably place the contact directly on top of the gate, making it possible to pack transistors closer together without changing their internal dimensions. At the same time, chipmakers worked to reduce the number of parallel fins needed by making them taller, finding ways to reduce the risk of them collapsing during manufacture.
The industry now is looking to more radical changes in the layout of circuitry that surrounds the core transistors, further increasing the gap between the names given to process nodes and physical dimensions of the actual structures found on-chip.
Several years ago, originally as part of its proposal for N3 or 3nm-class processes, Belgian research institute Imec proposed burying power-supply lines under the transistor layer. Today, the power-supply lines interfere with logic routing, not least because they need to be relatively large so current pulses caused by high-frequency switching do not distort or break them.
Though burying the power rails can seem an obvious choice from the circuit designer's perspective, it is not an easy one for chipmakers to make. Benjamin Vincent, senior manager of the semiconductor process and integration at Lam Research subsidiary Coventor, says bringing metals into the production flow at that point "is something that the entire semiconductor industry has been avoiding for decades." The high-conductivity metals that will be needed can easily contaminate silicon surfaces, disrupting transistor formation.
By the end of the decade, the IRDS committee expects the industry to embrace not just buried power rails, but other ideas that pack transistors into a smaller area by exploiting the third dimension. CEA-Leti and Imec have recommended various methods for stacking transistors on top of each other. One leading candidate for the so-called 1.5nm process is Imec's CFET, which places the two complementary transistors used for most of today's logic in a vertical stack to achieve a near-50% saving in area.
There is a precedent for extensive vertical integration. Flash-memory suppliers demonstrated they can stack more than 100 memory cells vertically. Similar structures may beckon for logic transistors, though it will require another wave of manufacturing innovation to pull off.
"With stacked approaches, all the critical-dimension control requirements we had in previous technologies in the horizontal direction now move into the vertical direction," says Vincent. With this vertical 3D approach, no longer will the gate length be controlled by complex and expensive lithographic methods; instead, it will rely on accurate deposition of films to define the channel length.
Not surmounting these manufacturing challenges will likely bring Moore's Law to an earlier-than-expected finish. However, the IRDS committee and chipmakers see the renewed emphasis on topological "cleverness" in place of conceptually simpler area scaling as being the way to keep up with the decades-old law and pave the way to a 1nm process even if the gates, wires, and other structures on-chip turn out to be 10 times bigger than the claimed measurement.
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