Over the past couple of process nodes, the chip industry has come to grips with the fact that Moore's Law is slowing down or ending for many market segments. What isn't clear is what comes next, because even if chipmakers stay at older nodes, they will face a series of new challenges that will drive up costs and increase design complexity.
Chip design has faced a number of hurdles just to get to this point, including a performance ceiling for processors and power limitations for all types of chips. There are issues involving RC delay, various types of noise, and increased challenges around photomasks and lithography. Through all of this, the drive to smaller nodes has paved the way to many of the answers. But as complexity and cost continue to skyrocket at each new node, the value of scaling no longer applies to the majority of designs, and the economic basis for scaling erodes for all but the largest-volume chips.
"In the past 35 years, the semiconductor industry and the EDA/IP industry have been spending most of their precious talents and resources readying and porting designs to new process nodes, generations after generations," states Chi-Ping Hsu, executive director at Avatar Integrated Systems. "Moore's Law definitely brought significant integration and scaling that were never imaginable before. But at the same time, it sucked all the talent to do mostly scaling/porting/integration type of engineering, instead of new innovations."
While the death of Moore's Law has been predicted for many years, it's certainly not the end of the road. In fact, it may be the opposite. "The end of Moore's Law could be the best thing that has happened in computing since the beginning of Moore's Law," said R. Stanley Williams, research scientist for HP Labs. "Confronting the end of an epoch should enable a new era of creativity." (Computing in Science & Engineering, IEEE CS and AIP, March/April 2017).
Or as Russell Klein, HLS Platform program director for Mentor, a Siemens Business, puts it, "If the design is unable to take advantage of a smaller geometry silicon processes, then designers will need to find creative ways to address this gap."
From Semiconductor Engineering
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