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New Computer Chip Manufacturing Method Squeezes More Onto Limited Wafer Space


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A scanning electron micrograph of a block copolymer film assembled on graphene/germanium chemical patterns with 90-degree bends. The scale bar is 200 nm.

University of Wisconsin-Madison and the University of Chicago researchers have developed a new way to pack more transistors in less space as their size approaches the atomic scale.

Credit: University of Wisconsin-Madison News

Researchers at the University of Wisconsin-Madison and the University of Chicago have developed a new method for packing more transistors in less space as their size approaches the atomic scale.

Team say they used directed self-assembly to offer a simpler, reproducible, and less expensive manufacturing approach.

The researchers note when chains of block copolymer moelcules self-assemble on a pre-pattern, they follow the pattern to form well-ordered features. These methods take advantage of a phenomenon called density multiplication. The researchers worked with a germanium wafer coated with a layer of virtually pristine graphene.

They note when they directed the block copolymer to self-assemble, it did so in a way that enhanced the resolution of the original template by a factor of 10, compared to a factor of four for the best previous enhancement by density multiplication.

The University of Chicago's Paul Nealey says the method is fast and reduces the process to lithography and plasma etching. "These templates offer an exciting alternative to traditional chemical patterns composed of polymer mats and brushes, as they provide faster assembly kinetics and broaden the processing window, while also offering an inert, mechanically and chemically robust, and uniform template with well defined and sharp material interfaces," Nealey says.

From University of Wisconsin-Madison News
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