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Stanford Team Combines Logic, Memory to Build a 'high-Rise' Chip


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four-layer prototype chip, illustration

The four-layer prototype high-rise chip built by Stanford engineers includes logic transistors on the bottom and top layers and two layers of memory in between.

Credit: Stanford University

Stanford University researchers say they have developed a method for creating high-rise chips that could outperform conventional single-story logic and memory chips. Their approach involves building layers of logic atop layers of memory to create a tightly interconnected high-rise chip. Many thousands of nanoscale electronic elevators would move data between the layers much faster, using less electricity, than the wires connecting existing single-story logic and memory chips.

The researchers' innovation leverages new technology for creating transistors, a new type of computer memory that lends itself to multi-story fabrication, and a technique to build these logic and memory technologies into high-rise structures in a new way. "With further development, this architecture could lead to computing performance that is much, much greater than anything available today," says Stanford professor Subhasish Mitra.

The researchers also demonstrated how to put logic and memory together into three-dimensional structures that can be mass produced. "With this new architecture, electronics manufacturers could put the power of a supercomputer in your hand," says Stanford professor Philip Wong.

From Stanford University
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Abstracts Copyright © 2014 Information Inc., Bethesda, Maryland, USA


Comments


Kal Gandikota

RRAMs so close to logic-dies would definitely increase the performance of these Systems-on-Stacks. By sandwiching RRAM between two logic layers, there will be considerable reduction in hot-spot effects too. Also un-wanted parasitic effects could be reduced.

If chips like these are mass-produced, they would accelerate research in Neuromorphic computing. Wonder what are the applications of these chips created at Mitra/Wong Lab of Stanford University? If there was some ROI, by now big Semi companies would have Fabs for the same, isnt it? Hence, what are the obstacles from commercializing this technology?

BTW, I did a pet-project to come up with adiabatic logic gates based of 21 multiplexers for similar CN+CMOS chips in 2005. At that time, there were no effective EDA tools to construct these chips. Wonder what EDA software tools they used to build this chip at this Stanford lab?

I agree with some thinkers that Quantum effects could affect the chip and its data integrity. Architecturally, the problem could be solved by implementing self-repair techniques (especially using error detection/correction/may be even Forward-Error Correction) Also, using fluid cooling techniques might reduce thermal effects which in turn reduce quantum effects. (As part of my neuromorphic studies, I came to know that there is a blood-brain barrier system in biological creatures. May be something similar could be constructed).

From another post at Kurzweilai, a commentator said,
As for coolingthere are a variety of methods that could be used. I like to keep things simple, so having coolant channels throughout the chip makes the most sense to me.
To avoid accidental shorting, they could use a non-conductive fluid like this mineral oilnow being explored by the NSA for project PRISM...........
http://www.datacenterknowledge.com/archives/2014/09/04/nsa-exploring-use-mineral-oil-cool-servers/


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