The Hybrid Memory Cube Consortium recently announced the final specifications for 3D dynamic random-access memory (DRAM), which is designed to boost performance for networking and high-performance computing applications.
Hybrid Memory Cube technology stacks multiple volatile memory dies on top of a DRAM controller. The DRAM is connected to the controller via Vertical Interconnect Access technology, a method of passing an electrical wire vertically through a silicon wafer.
"We took the logic portion of the DRAM functionality out of it and dropped that into the logic chip that sits at the base of that 3D stack," says Micron's Mike Black. "That logic process allows us to take advantage of higher performance transistors...to not only interact up through the DRAM on top of it, but in a high-performance, efficient manner across a channel to a host processor."
The logic layer serves as both the host interface connection and the memory controller for the DRAM sitting on top of it, Black says. Moreover, Hybrid Memory Cube technology reduces the tasks that a DRAM must perform so that it only drives the through-silicon vias, which are connected to much lower loads over shorter distances, notes analyst Jim Handy.
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