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Design Reduces Nanowire Transistor Footprint


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Tunnel field effect transistors

Tunnel field effect transistors

Credit: GigaOm

A*STAR Institute of Microelectronics researchers have integrated two transistors onto a single vertical silicon nanowire, which they say could further push the areal density limit of nanowire transistors.

The researchers, led by A*STAR's Xiang Li, used wrap-around gates, known as gate-all-around gates, to make the new device. The gates consist of a vertical cylinder with a nanowire in the middle, and the researchers say they are much better at controlling the transistor current than traditional planar gates.

The gates were used to develop a logic device that uses just one nanowire. The logic device functions as an "AND" digital gate, but uses only 50 percent of the area it would otherwise need. In addition, the researches say the stacked gate arrangement could be useful for enabling tunnel field effect transistors (TFETs). Since TFETs rely on the tunneling of electrons across a barrier instead of the thermal activation of elections, they turn on quickly and run efficiently.

Li notes that the tunnel junction a TFET needs could be formed between the two gates of the dual-gate nanowire geometry, enabling an extremely compact deployment. The dual-gate design also could be employed for non-volatile memory.

From EE Times Asia 
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