Hierarchical hardware coherence that remains transparent to application programs could be used to solve the scaling problem for next-generation processors, according to a Semiconductor Research Corp. (SRC) study.
The technique scales as the square root of the number of cores, adding as little as 2 percent latency for processors with as many as 512 cores. Moreover, traffic, storage, and energy consumption would grow very slowly as cores are added, enabling future processors to continue using direct-write caches with hardware coherence that is transparent to application programs.
"These results will change the direction of computer architecture, by assuring designers that cache coherence will not hit the wall," says SRC's David Yeh. "All the right techniques are available today--you don't need new tricks to be invented, but just need to wisely use the technologies that are already available."
SRC says the study shows that the roadmap to future massively parallel multi-core processors is clear and unobstructed.
From EE Times
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