Hewlett-Packard's (HP's) research division is developing Corona, a manycore chipset designed to outperform existing average-sized high-performance computing (HPC) clusters.
The design would offer a significant performance boost, and if implemented, could fulfill the promise of exascale computing. Corona consists of a 256-core central processing unit (CPU), an optical memory module, integrated nanophotonics, and three-dimensional chip stacking employing through-silicon-vias, which could deliver 10 teraflops of performance at peak output.
The processor is divided into 16 quad-core clusters, with an integrated memory controller on every cluster. The memory module is a separate chip stack consisting of dynamic random access memory chips, plus the optical die and interface. The main function of Corona's optical interconnect is to solve the worsening bytes-to-flop ratio that has limited HPC systems. The primary causes for the poor ratio are the pin limitations on multicore processors, the inability to extend chip-level communication links across an entire node or computer, and the energy costs of electrical signaling.
Using the SPLASH-2, the second version of the Stanford Parallel Applications for Shared Memory benchmark suite, HP's researchers demonstrated that Corona offers a performance improvement of two to six times compared to a similar system equipped with an electrical interconnect.
From HPC Wire
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Abstracts Copyright © 2012 Information Inc. , Bethesda, Maryland, USA
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