The semiconductor industry is moving toward three-dimensional (3D) chip design, stacking dies and moving data from one layer to another.
Some researchers are using though-silicon vias (TSVs) to create 3D chip designs. Dies currently are connected to each other with TSVs, ensuring that the interconnects between devices are microns long instead of millimeters long, cutting signal latency by orders of magnitude and reducing power consumption.
In fact, consultant Herbert Reiter says developing 3D chips that consume 50 percent less power than two-dimensional (2D) chips is an achievable goal. Sematech's Sitaram Arkalgud notes that layering memory on top of chips is widely viewed as another potential application for 3D technology. He says the first generation of volume-production 3D devices should appear in 2013.
However, although 3D chips may not reach the market until 2013, a variant of the technology, known as 2.5D, already is in production. The 2.5D technology has certain characteristics that make it more attractive than 3D, which still has issues with heat dissipation and interference caused by the copper in the TSVs, says Xilinx's Liam Madden.
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