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UCLA Receives $5.5m For Work on High-Speed, High-Capacity Memory

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STT-RAM tunnel junction

Schematic representation of magnetic tunnel junction memory cells developed by a UCLA Engineering team. Acronyms: free layer (FL); top-pinned layer (TPL); and bottom-pinned layer (BPL).

Credit: UCLA

University of California, Los Angeles (UCLA) researchers recently received a $5.5 million U.S. Defense Advanced Research Projects Agency grant to continue developing technology that could lead to low-power computers that need almost no start-up time when activated.

The researchers are working on a high-speed, high-capacity computer memory, known as spin-transfer torque magnetoresistive random access memory (STT-RAM), which is compatible with current standards and has advantages over other types of memory such as dynamic random access memory (DRAM) and static random access memory (SRAM). The researchers say that STT-RAM could combine the benefits of DRAM and SRAM, as well as flash memory common in USB drives, into a single scalable memory technology with great endurance and extremely low power requirements. The researchers recently completed the first phase of the project a year ahead of schedule by meeting the standards for speed, energy consumption, and stability for STT-RAM bits.

As part of the second phase, the team will improve the energy and stability metrics and build prototype STT-RAM chips. "An important emphasis of the second phase . . . will be statistical studies needed to facilitate integration with CMOS to realize a product," says UCLA researcher Pedram Khalili.

From UCLA Newsroom
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