Sign In

Communications of the ACM

Research highlights

Technical Perspective: Silicon Stress

View as: Print Mobile App ACM Digital Library Full Text (PDF) In the Digital Edition Share: Send by email Share on reddit Share on StumbleUpon Share on Hacker News Share on Tweeter Share on Facebook

Moore's Law, which predicts the doubling of transistor density every two years or so, has been the mainstay of the ubiquitous proliferation of semiconductor electronics and the mobile revolution that has changed our lives for the better since the invention of the transistor by Shockley et al. in 1949 and its application to the integrated circuit by Kilby in the 1950s.

For the past several decades, we have been scaling relentlessly using Dennard's constant electric field scaling method and succeeded in making our chips faster, smaller, and cheaper. Implicit in this evolution is the assumption that we can print these circuits in an economical manner. This assumption is now in question as we have reached dimensions that are significantly below the resolution of the light used to print these features. While we have employed tricks to print these sub-wavelength features, they come at a cost that threatens the expectation of lower cost per circuit. In fact, some project an increased cost per function, which of course begs the question: "Why scale any further?"

Three-dimensional integration (3Di) offers some relief here. It is important to point out that 3Di does not make either a faster transistor or a cheaper transistor per se, but offers the possibility of integrating mature technologies to achieve effective improvements in effective arial transistor density, lower die-to-die latency, and a high degree of componentization by integrating separately optimized and hence less complex technologies. This approach promises to extend the Moore's Law expectation at least for a few more generations.

The TSV allows signals and power to pass through an entire silicon layer and is perhaps the most distinguishing feature of 3D stacking.

There are many embodiments of 3Di, which require the stacking of either partially functional dice or even wafers. A common feature of all these different embodiments is the Through Silicon Via (TSV). The TSV literally allows signals and power to pass through an entire silicon layer and is perhaps the most distinguishing feature of 3D stacking. TSVs tend to be rather large compared to the other features in the chip. Moreover, they are lined with thick dielectrics and filled with conductive materials that have a high coefficient of thermal mismatch with respect silicon. The consequence of the introduction of these large dissimilar features is the potential to cause significant stresses in the silicon that can cause structural defects and even failure in the silicon. It is also possible to modulate the electrical properties of the silicon devices, although that may be a less severe effect.

The following paper by Jung et al. is a thorough analysis of the stresses that can result from the introduction of a TSV in silicon. The authors have developed a fairly comprehensive and yet simple method to apply linear superposition to estimate the thermo-mechanical stresses that these TSVs can introduce. The analysis also can be used to estimate a simplified metric called the Von Mises stress that is a measure of mechanical stability. This approach can be used to design stable and reliable TSVs and promises to be a valuable tool in the design of 3D chips.

Back to Top


Subramanian S. Iyer ( is an IBM Fellow and Director of System Scaling Technology, Microelectronics Division, at the Systems and Technology Group, Hopewell Junction, NY.

Copyright held by author.

The Digital Library is published by the Association for Computing Machinery. Copyright © 2014 ACM, Inc.