Energy efficiency is the new fundamental limiter of processor performance, way beyond numbers of processors.
There appears to be a small error in figure 7: presumably the x-axis label "2008" should be "2018".
Looks like 3D transistors are going to have to be stacked and layered, or they are going to run out of room for more, unless they feel more isn't what they need. I could see that being possible after 10 years from now, but for now after 3D transistors become mainstream, they will have to do this instead of continuing to make them smaller, after they get to 11 nm process and smaller.
3D transistors are called 3D because they are not planar transistors. This does not imply that 3D transistors are stacked (today). Nevertheless, nothing stops you from stacking planar or 3D transistors monolithically or polylithically. One thing to consider though, by stacking transistors, 3D or not, it increases the power density; that is, amount of power consumed per unit area, making heat removal even mor challenging.
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