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Technical Perspective: Integrating Flash Devices


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Flash memory nowadays seems to be in every discussion about system architecturenot only in mobile devices from phones to notebook computers, but also in servers, from Web servers to blades and database systems. Sure enough, flash memory boasts multiple qualities and advantages over traditional mass storage, disk drives with rotating platters and moving access arms. These include no noise or vibration, lower power consumption and cooling requirements during both active and idle times, faster access times, and lower cost when calculated with a focus on access performance rather than on capacity. For example, a "flash disk" device providing a standard interface and form factor of traditional SATA disk may cost five times more than a traditional SATA disk, but if it permits 100 times more read operations per second, the cost for access performance is 20 times less. Similarly, flash memory devices offer tremendous advantages over traditional disk drives in terms of power and energy relative to access performance.

On the other hand, flash memory still suffers from two principal weaknesses: reliability and cost relative to capacity. Thus, a system architect is tempted to combine traditional RAM and traditional disk drives with flash memory. The RAM provides write endurance by absorbing the data traffic coming from the CPU caches; omitting RAM in a system architecture and backing up CPU caches with flash memory would lead to very unreliable or expensive computing systems. The traditional disk drives provide cost-efficient storage capacity; many studies have shown that a large fraction of any data collection is rarely accessed after a short initial period of creation and repeated activity. In fact, disk hardware could be divided into capacity-optimized drives, often targeted at consumers, and performance-optimized drives, often targeted at enterprises. Multi-disk strategies could be similarly divided, with RAID-5 and -6 optimized for minimal overhead, minimal power, and maximal capacity and with RAID-1 optimized for performance.

In discussions and designs, flash memory is placed between RAM and disks. Thus, the traditional two-level memory hierarchy (ignoring CPU caches and archival tapes) becomes a three-level hierarchy. For most applications, rewriting the source code to accommodate a deeper memory hierarchy does not make sense. Thus, the flash memory must be integrated in such a way that its presence is hidden except for the performance or cost advantage. One exception may be database management systems, which manage very large data volumes and are thus constantly being updated to take the best advantage of available hardware. For example, researchers and vendors are investigating challenges and opportunities due to deep CPU caches, many-core processors, transactional memory, and flash memory.

Roberts, Kgil, and Mudge represent a perspective that assumes no change in application software, meaning all adaptations for deep memory hierarchy and for flash memory are in the lower levels of system software. Multiple interesting and promising techniques are explored, for example, increasing reliability of multi-level flash memory by using individual pages in single-level mode rather than immediately declaring them bad blocks. This novel technique for graceful degradation of flash memory capacity, if widely adopted in future implementations of the flash translation layer, could greatly increase reliability and cost effectiveness, and speed the adoption of flash memory in all kinds of servers. The race is on among techniques that give flash memory the required reliability and endurancecandidates include over-provisioning, hardware techniques such as those presented here, and software techniques such as a flash translation layer akin to a log-structured file system.

The authors introduce and compare three basic architectures of using flash memory in the memory hierarchy: as "extended system memory," as "storage accelerator," and as "alternative storage device." This characterization resonates with earlier work on the Five-Minute Rule and flash memory (ACM Queue 2008). The authors tie these usage models to hardware interfaces, namely memory, PCI, and disk interfaces such as SATA. After reviewing these approaches, the authors synthesize a proposed architecture for a flash-based disk cache. The proposed memory controller partitions the flash memory into separate regions for reading and writing in order to accommodate the need to erase large blocks prior to writing. Future improvements, for example, adaptation of generational garbage collection as proposed for log-structured file systems, will likely build on this foundation. The proposed "flash cache hash table," held in RAM, permits efficient mapping of pages to locations in flash memory; one wonders whether this function could be integrated in the virtual memory management already ubiquitous in operating systems.

The authors present results of a detailed simulation study of their proposed architecture using a full-system simulator. Rather than simply add flash to a system including traditional RAM and traditional disks, they reduce RAM for equal die area before comparing the RAM-and-flash system with the traditional RAM-only system. Equal power consumption could be an alternative metric but is left for future study. Similarly, secondary software effects are omitted, for example, faster access times leading to shorter delays due to virtual memory faults or misses in the buffer pools of file system or database server, such that a lower multi-programming level can mask all those delays, which in turn reduces memory contention and thus the RAM required in the system.

Nonetheless, the results demonstrate that with flash memory in a memory hierarchy, less power and cooling can still result in higher processing bandwidth, and that the proposed programmable controller for flash memory can extend the expected lifetime for a given access rate. With those results, the proposed techniques represent a step toward more efficient storage, servers, and data centers, reducing costs for data center operation and environment emissions.

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Author

Goetz Graefe (goetz.graefe@hp.com) is an HP Fellow and member of the Advanced Database Group at Hewlett-Packard Laboratories

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Footnotes

DOI: http://doi.acm.org/10.1145/1498765.1498790


Copyright held by author.

The Digital Library is published by the Association for Computing Machinery. Copyright © 2009 ACM, Inc.


 

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