A team of Google researchers claim they've fine-tuned a technique to automate the placement of on-chip transistors in the design of an upcoming, previously announced generation of Google's Tensor Processing Units, circuits developed specifically to accelerate AI.
If made publicly available, the technique could enable cash-strapped startups to develop their own chips for AI and other specialized purposes. Moreover, it could help to shorten the chip design cycle.
The team describes its work in "A Graph Placement Methodology for Fast Chip Design," published in the journal Nature.
The solution uses a reinforcement learning method that can learn from experience to become both better and faster at the physical floorplanning of new chips.
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